This is a U.S. national stage of International application No. PCT/DE00/00276 filed 1 Feb. 2000.
This patent application claims priority of German Patent Application No. 19908414.9 filed 26 Feb. 1999, the disclosure of which is hereby incorporated by reference.
(1) Field of the Invention
The invention relates to an optimized bus connection for acceptance of bus transactions.
(2) Description of Related Art
The most diverse bus transactions take place in a processor system. Such bus transactions can be classified as those transactions which must be executed in a strictly logical sequence, and can be classified as those transactions which do not have to be executed in a strictly logical sequence.
Bus connections provided with a temporary store operating according to the FIFO principle are known for acceptance of bus transactions. In the temporary store operating according to the FIFO principle, bus transactions are temporarily stored in the sequence of their arrival in the sequence of their arrival and subsequently read out and executed in corresponding sequence, regardless of whether they must be or do not have to be executed in strictly logical sequence.
During bus transactions, it is frequently necessary to wait for results of other bus transactions, for example in order to be able to operate further with updated parameters. Because of the circumstance that the bus transactions are executed in the sequence of arrival, bus transactions which are independent of such transactions must nevertheless wait until the transactions that arrived earlier have been completed. The overall result is slowing and thus loss of performance of the processor system.
One object of the present invention is to provide an optimized bus connection, by which the working speed of a processor system is accelerated and thus its performance capability is increased.
This and other objects are attained in accordance with one aspect of the invention directed to an optimized bus connection for acceptance of bus transactions, provided with a first store operating according to a FIFO principle, in which bus transactions arriving from a higher-level processor system for execution by the optimized bus connection are temporarily stored in their sequence of arrival. A first functional section is coupled to an output of the first store for classifying the bus transactions temporarily stored in the first store, and including means for classifying those transactions that must be executed in a strictly logical sequence as a first class of transactions, and those transactions that do not have to be executed in a strictly logical sequence as a second class of transactions. A second functional section is coupled to an output of the first functional section and comprises at least first and second functional lines disposed in parallel, wherein the first functional line is allocated to the first class of transactions, and is provided with a storage structure functioning according to the FIFO principle, and wherein the second functional line is allocated to the second class of transactions, and has a storage structure suitable for random accesses. A third functional section, with an execution unit, is coupled to the functional lines of the second functional section, and comprising means for organizing the transactions allocated to the at least first: and second function lines of the second functional section into a serial sequence for forwarding to the higher-level processor system, wherein the organizing means of the execution unit moves a transaction of the second class ahead of a transaction of the first class, depending on a state of the higher-level processor system.
Such a bus connection classifies and typifies the arriving bus transactions and allocates them to respective functional lines disposed in parallel. Depending on the class or type of a transaction, the transactions are temporarily stored in the various functional lines in such a way that, on the one hand, they can be treated according to their class or type and, on the other hand, they are sufficiently separated from one another that an adapted sequence can be selected in the sequence of execution. Contributing to this is the fact that some functional lines have a parallel structure. Thus transactions can be moved to the front with the inventive bus connection, so that waiting times until completion of a previously arrived transaction can be eliminated in many cases. The result is acceleration of the mode of operation and thus increased performance capability of a processor system.
Accordingly, not only are transactions pending for execution separated according to whether or not they must be executed according to a strictly logical sequence, but also the transactions that do not have to be executed strictly according to a logical sequence are further separated according to whether they are transactions of the read or write type. Read transactions in particular are determining for the performance of an overall system. They must therefore be given special priority in execution.
As explained in the foregoing, the inventive bus connection eliminates congestion effects which can occur among transactions pending for execution. In the absence of congestion effects, it is possible that entire functional lines will remain almost empty, because arriving transactions can be executed immediately. In order to save further on time needed to transport transactions through the so-called empty functional lines, advantageous embodiments of the invention are provided with shortcuts which bypass the so-called empty functional lines.